1. Field of the Invention
The present invention relates to semiconductor memories and more particularly, to an integrated circuit, three-element, charge pumped, automatic refresh, dynamic storage, random access memory cell.
2. Description of the Prior Art
In the prior art, semiconductor random access memories are well known. Dynamic semiconductor memories utilize charge stored in the capacitance between the device and the substrate to represent a particular value of information being stored. In order to retain the information in storage, it is then necessary to counteract the effect of the various leakage phenomena which cause the value of the stored charge to change.
The prior art has solved this problem by utilizing various "refreshing" schemes. Dynamic Random Access Memory Cells are described in some detail in Chapter 5, Section 5.3 from pages 120-124, in the volume "Semiconductor Memory Design and Application" by G. Luecke et al., published by McGraw-Hill Book Company as a part of the Texas Instruments Electronics Series.
The prior art has also disclosed the use of a phenomenon known as "charge pumping" in a random access memory cell. One such example has been disclosed in "Semiconductor Memory Design and Application", supra, at page 132, Section 5.6.2, pages 132-134, in which the charge pump phenomenon was employed in a crosscoupled RAM cell utilizing semiconductor load devices. A charge pump supply provided a constant current supply which was deemed to be an ideal load device, and which could be achieved with minimum geometry while still retaining the high load resistance.
In a paper delivered to the 1976 IEEE International Solid State Circuits Conference in February, 1976 and reported in the digest of technical papers at pages 132 and 133, an Automatic Refresh Dynamic Memory was disclosed by authors Harry J. Boll, et al. of the Bell Laboratories. This automatic refresh cell comprised approximately six devices, although an experimental device appeared to utilize only five. The circuit operated at voltages of from 6 to 8 volts on the refresh line.
An interesting variation on the dynamic RAM cell was described in Section 5.6.3 of the Luecke et al. book, supra, at pages 134, 135. A three transistor MOS cell, originally disclosed by Walther and McCoy in ISSCC 1972, Digest of Technical Papers, pp. 14-15, utilized the parasitic gate capacitance to "refresh" a storage capacitor during each read-write cycle. The use of the parasitic gate to substrate capacitance as the storage element in a three transistor dynamic MOSFET cell was described in the book "Physics of Computer Memory Devices" by Middelhoek, et al., published by Academic Press.
It is a continuing goal of designers to produce a random access memory device of low power, high speed, and small size, which can most efficiently utilize the available semiconductor substrate. Further, it has been deemed desirable to have such devices operating at voltages in the range of 5 volts or less. Obviously, the polarity of the operating voltages is a function of the technology to be employed, whether it be n-channel or p-channel.